Z-DSPClock Dilly DSP card.A Z-DSP is required to use.
For any algorithm, the machine lock for synchronization must be entered at the middle of the Z-DSP's 3 CV input in the middle of the VC-P2 Jack.The corresponding knob (VC-DSP2) should be located at 0.The clock that you enter for synchronization does not react correctly with a short triger signal.Enter the length of the clock's gate set to 25 %-50 %.
The speed of the clock that can be used per BPM on the input clock is different:
- BPM60 or lower or sixteen minutes of clock, enter a pulse width of 50 %.
- BPM61-120 Enter a 4-minute clock with a pulse width of 25 %-50 %.
- BPM120-180 Enter a 4-minute or 2-minute clock with a pulse width of 25 %
- Enter a BPM180 or a 2-minute or full-tone clock clock with a pulse width of 25 %
The algorithm is as follows:
- 1. Mono L/R Clocked Taps
- 2. Mono Clocked Low Pass
- 3. Mono Clocked Fdbk + HPF
- 4. Mono Clocked Bandpass
- 5. Dual Clocked Delays
- 6. Clocked Ping Pong
- 7. Dual Clocked HPF
- 8. Dual Clocked Feedback